The present invention relates generally to a nonvolatile semiconductor memory device. More particularly, the present invention relates to a nonvolatile semiconductor memory device which stores multi-state data using memory cell transistors having floating gates.
An electrically erasable and programmable ROM (EEPROM) has memory cells each comprising a single transistor having a floating gate and a control gate. Using such memory cell transistors with a double gate structure, data is written in each memory cell by injecting hot electrons, generated in the drain region, into the floating gate. Data is read out by detecting the operational characteristic of the memory cell transistor which varies in accordance with the charge that is stored in the floating gate.
FIG. 1 is a schematic plan view partially showing memory cells of a nonvolatile semiconductor memory device. FIG. 2 is a cross-sectional view taken along the line 2--2 in FIG. 1. Each memory cell is embodied in the form of a transistor with a split gate structure, where the floating gate and the control gate are so arranged that a part of the control gate covers the floating gate.
A plurality of isolation regions 2 each comprising an oxide film (LOCOS) which is relatively thick, and device regions are alternately defined on the surface of a P type silicon substrate 1. A first oxide film 3 is located on the silicon substrate 1, with a floating gate 4 so arranged on the oxide film 3 as to lie over the adjoining isolation regions 2. The floating gate 4 is provided for each memory cell. The floating gate 4 has sharp projections at its end portions. A second oxide film 5, which is thick in the center, is located on the floating gate 4. The projections of the floating gate 4 prevent an electric field from being concentrated at the end portions of the floating gate 4 at the time of erasing data.
Disposed over the silicon substrate 1 is a control gate 6 that has a first portion which covers the floating gate 4 and a second portion,located on the oxide film 3. The floating gate 4 and the control gate 6 are so arranged as to be symmetrical to each other over adjoining columns of memory cells.
An N type first diffusion layer ? is defined in the surface of the substrate region between the adjoining control gates 6. An N type second diffusion layer 8 is defined in the surface of the substrate region between the adjoining floating gates 4. The floating gate 4, the control gate 6, the first diffusion layer 7 and the second diffusion layer 8 form a memory cell transistor. Located on the control gate 6 is a third oxide film 9 on which an aluminum line 10 is laid in such a way as to intersect the control gate 6. The aluminum line 10 is connected via a contact hole 11 to the first diffusion layer 7.
The ON-resistance between the source and drain of the aforementioned memory cell transistor varies in accordance with the amount of charge stored in the floating gate 4. Multi-state data can therefore be stored in each memory cell transistor by controlling the amount of charge stored in the floating gate 4 in such a way that the ON-resistance of the memory cell transistor varies stepwise. For example, four-state (2 bits: "00", "01", "10" and "11") data can be stored in a single memory cell transistor by controlling the amount of charge stored in the floating gate 4 in such a manner that the ON-resistance of the memory cell transistor varies in four steps.
FIG. 3 is a schematic circuit diagram of a prior art nonvolatile semiconductor memory device using the memory cells in FIG. 1. Referring to FIG. 3, the memory cells are arranged three rows by three columns. The control gate 6 of each memory cell transistor 20 is connected to a word line 21, and the first diffusion layer 7 and the second diffusion layer 8 are respectively connected to a bit line 22 and a source line 23. Each bit line 22 is connected to a data line 25 via an associated select transistor 24, while each source line 23 is connected to a power line 26. Normally, the control gate 6 of each memory cell transistor 20 serves as the word line 21, and the second diffusion layer 8 serves as the source line 23. Further, the aluminum line 10 connected to the first diffusion layer 7 serves as the bit line 22.
A row decoder 27, connected to the individual word lines 21, selects one of the word lines 21 in response to row selection information. As a result, a group of memory cell transistors 20 in a specific row are enabled. A column decoder 28, connected to the individual select transistors 24, turns on one of the select transistors 24 in response to column selection information which enables a group of memory cell transistors 20 in a specific column. The row decoder 27 and the column decoder 28 operate to enable one of a plurality of memory cell transistors 20 and connect the selected transistor to the data line 25.
Writing multi-state data into the memory cell transistors 20 requires a high writing precision for which injection (writing) of charge and verification (reading) of the amount of charge injected are alternately repeated in a short cycle. That is, data reading from the memory cell transistors 20 is carried out while writing data in the memory cell transistors 20. When the read data matches with the desired written data, the writing operation stops.
In the writing operation of the selected memory cell transistor 20, as a ground potential (e.g., 0 V) is applied to the data line 25 and a power supply potential for writing (e.g., 12 V) is applied to the power line 26, charge is injected to the floating gate 4 of the memory cell transistor 20.
In the reading operation of the selected memory cell transistor 20, as a power supply potential for reading (e.g., 2 V) is applied to the data line 25 and the ground potential (e.g., 0 V) is applied to the power line 26, a sense amplifier (not shown) detects the resistance of the transistor 20 when the memory cell transistor 20 is turned on. FIG. 4 is a block diagram of the sense amplifier. The sense amplifier includes a pair of load resistors 31 and 32, a pair of current amplifiers 33 and 34, a reference transistor 35, a constant potential generator 36, a differential amplifier 37 and a decision control circuit 38.
The pair of load resistors 31 and 32, connected to a power supply, have the same resistance. The current amplifier 33, connected to the load resistor 31 and the data line 25, includes a transistor and an inverter. The current amplifier 34, connected to the load resistor 32 and the reference transistor 35, includes a transistor and an inverter. The reference transistor 35, connected between the current amplifier 34 and ground, changes the resistance in response to a reference potential V.sub.RG which is applied to the gate. The constant potential generator 36 generates the reference potential V.sub.RG corresponding to multi-state data to be stored in the memory cell transistor 20, and supplies that reference potential V.sub.RG to the gate of the reference transistor 35. For the memory cell transistors 20 each capable of storing 4-state data (2 bits), for example, the constant potential generator 36 generates three kinds of,gate potentials V.sub.RG so that the resistance of the reference transistor 35 varies in three steps.
The differential amplifier 37 has a first input terminal connected to a node between the load resistor 31 and the current amplifier 33, and a second input terminal connected to a node between the load resistor 32 and the current amplifier 34. The differential amplifier 37 compares potentials V.sub.B and V.sub.RL at the nodes with each other and sends a comparison output CO to the decision control circuit 38.
The decision control circuit 38 controls the constant potential generator 36 and determines the multi-state data from the comparison output CO from the differential amplifier 37 to reproduce the multibit data. In the case of 4-state information, for example, an intermediate one of three-level reference potentials, namely a high potential, an intermediate potential and a low potential, is generated first to determine whether the upper bit is "1" or "0". Then, the high potential or low potential is generated in accordance with the result of the decision on the upper bit in order to determine whether the lower bit is "1" or "0".
When data is read from the memory cell transistor 20, as shown in FIG. 4, the source of the memory cell transistor 20 is grounded and the load resistor 31 and the memory cell transistor 20 are connected in series between the power supply and the ground via the current amplifier 33. Likewise, the load resistor 32 and the reference transistor 35 are connected in series between the power supply and the ground via the current amplifier 34. Therefore, the potential V.sub.B at the node between the load resistor 31 and the current amplifier 33, is determined by the ratio of the resistance of the load resistor 31 to the drive performance of the memory cell transistor 20. Likewise, the potential V.sub.RL at the node between the load resistor 32 and the current amplifier 34, is determined by the ratio of the resistance of the load resistor 32 to the drive performance of the reference transistor 35. It is possible to determine in what range the resistance of the memory cell transistor 20 lies with respect to the resistance of the reference transistor 35 by comparing the determined potentials V.sub.B and V.sub.RL using the differential amplifier 37.
Since the sense amplifier reads data in accordance with the ratio of the resistance of the memory cell transistor to the resistance of the load resistor 31 and the resistance of the reference transistor 35 to the resistance of the load resistor 32, it is important to precisely set the resistances of the load resistors 31 and 32. The resistances of the load resistors 31 and 32 are normally set in accordance with the resistance of the memory cell transistor 20. When the resistances of the load resistors 31 and 32 are shifted to the larger side or smaller side than the optimal values, the potentials V.sub.B and V.sub.RL at the nodes show small changes with respect to a change in the resistance of the memory cell transistor 20. Such a small variation makes it difficult for the differential amplifier 37 to accurately output the comparison result.
The reference transistor 35 and the constant potential generator 36 should keep operations stable in order to prevent the differential amplifier 37 to always acquire the stable reference potential V.sub.RL. However, there is a variation, in the manufacture stage, in elements which constitute the constant potential generator 36. To always supply the stable gate potential V.sub.RG, therefore, a circuit is required for finely adjusting the potential of the constant potential generator 36. Such a circuit increases the circuit area of the sense amplifier and also increases the manufacturing cost, of the memory.